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Micrel, Inc.
The front end’s input impedance, with no matching
network, is close to 50 ? as shown in Figure 15. This gives
an input reflection coefficient of about -13dB. Although the
receiver does not require a matching network to optimize
MICRF507
The pre-filter and switched-capacitor filters in cascade
must pass the full IF bandwidth of the received signal. In a
zero-IF receiver such as the MICRF507 this bandwidth is
as follows:
the gain, a matching network is recommended for
harmonic suppression during transmission and for
improved selectivity in reception.
f BW = f OFFSET + f DEV +
r b
2
Sallen-Key Filters
Each IF channel includes a pre-amplifier and a pre-filter.
The preamplifier has a gain of 22dB. The IF amplifier also
removes DC offset. Gain varies by less than 0.5dB over a
2.0V to 2.5V variation in power supply.
The pre-filter is implemented as a three-pole Sallen-Key
low-pass filter. It protects the switched-capacitor filter that
follows it from strong adjacent channel signals and also
serves as an anti-aliasing filter. It is programmable to four
different cut-off frequencies as shown in Table 14.
where
f BW : Needed receiver bandwidth; f CUT above should
not be smaller than f BW [Hz]
f OFFSET : Total frequency offset between receiver and
transmitter [Hz]
f DEV : Single-sided frequency deviation [Hz]
r b : The bit rate in bits/sec
RSSI
PF_FC1
0
0
1
1
PF_FC0
0
1
0
1
Cutoff (3dB filter corner)
100kHz
150kHz
230kHz
340kHz
Table 14. Pre-Filter Bit Field
Switched Capacitor Filter
The main IF channel filter is a switched-capacitor
f CUT =
implementation of a six-pole elliptic low pass filter. This
meets selectivity and dynamic range requirements with
minimum total capacitance. The cut-off frequency of the
switched-capacitor filter is adjustable by changing the
clock frequency.
A 6-bit frequency divider, programmed by the ScClk[5:0]
field, is clocked by the crystal oscillator. Its output, which is
20 times the filter’s cutoff frequency, is then divided by 4 to
generate the correct non-overlapping clock phases needed
by the filter. The cut-off frequency of the filter is given by:
f XCO
40 ? ScClk
f CUT : Filter cutoff frequency
f XCO : Crystal oscillator frequency
ScClk: Switched capacitor filter clock, bits ScClk[4:0]
(bit 0 has a mandatory value of ‘0’).
For instance, for a crystal frequency of 16MHz and if the 6
bit divider divides the input frequency by 4, the cut-off
frequency of the SC filter is 16MHz/(40 x 4) = 100kHz. A
first-order RC low-pass filter removes clock frequency
components from the signal at the switched-capacitor filter
output.
Figure 16. RSSI Voltage
Figure 17. RSSI Network
Figure 16 shows a typical plot of the RSSI voltage as a
function of input power. The RSSI termination network is
shown in Figure 17. The RSSI has a dynamic range of
about 50dB from about -110dBm to -60dBm input power.
When an RF signal is received, the RSSI output increases
and can serve as a signal presence indicator. It could be
used to wake up external circuitry that conserves battery
life while in a sleep mode. Note that RSSI only functions in
Receive mode.
October 2, 2013
25
Revision 2.2
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